Last year, Mike Engelhardt – the creator of Linear Technology’s free LTSpice schematic capture and simulation software – came to Adelaide.
I went along to hear all about it.
It was all good fun, with lots of spruiking about how powerful these circuit modelling tools were, and what a terrific time-saver they were compared to the old methods of hacking up a breadboard to test a new design.
I skulked out of there feeling like a Troglodyte, determined to spend even more time in front of the computer and less time with pen, paper and soldering iron down the back shed.
Look up any number of sources if you want the good oil on why computer models will replace old circuit hackers like me.
What they never mention is that the real advantage of simulating circuits is that you can run them and make measurements in the background while sitting at your computer pretending to answer emails in the foreground.
So I hacked together a few circuits I was thinking about in LTSpice, and then the problems began. All the usual inexplicable and frustrating stream of inscrutable computer messages pinging you in the face and getting between you and the answer: –
“Analysis: Time step too small; time =0.00666736, timestep = 1.26211e-018: trouble with node “ramp””
Now it was all about the tool, and nothing about the circuit.
So I sent off my files to Mike Engelhardt via the local LT office, and after a couple of months and some prompting from me, the answer came back: –
“… it is difficult to correct other company parts, and there is an issue in the library of the NE555.
We have only two engineers including Mike Elgelhart to support LTSpice, so it is sometimes difficult to support all issues on LTSpice especially non-LTC parts libraries”
True, Wikipedia states that over a billion 555 timer ICs are produced each year, and I did find the 555 part in the LTSpice library, and all the other parts in my circuit are made by Linear Tech except for this old bipolar 555 (there is no library part for the more modern 7555 CMOS timer which I really wanted to use).
Also true is that LT have over 3700 employees world-wide, so two engineers dedicated to LTSpice doesn’t sound like much, particularly at the rate they produce sexy new parts that have to be entered into their libraries.
By this stage I’d already hacked up the usual breadboard on the bench at home and got it all working using solder and sweat.
Still and all, sniffing the solder is not something that’s easily hidden when I’m supposed to be at my computer doing management stuff!
I agree – simulation can be frustrating (read poorer value for effort than expected). In this regard it reminds me of my off quipped line abut innovation. Innovation is great but it is also very expensive and risky – so better make sure it is applied where the returns are highest.
So I simulate stuff – not every week. I normally use nutmeg (which is a distro of Spice with some extra’s around it) or our schematic capture tool ISIS (not the political outfit). I also generally use it for discrete circuits – if you simulate IC’s better check the model is based on the actual circuit for the IC rather than a ‘macro’ model.
Generally the problems you get with IC’s are less likely to be picked up in simulation.
Where the simulation comes into its own is that once a model of a circuit is made (and accurate) the testing is really quick. I designed a simple over-temperature shutdown for a battery recently. Being simple and cheap it was also a bit sloppy. The trip temperature varied with battery voltage and so did the hysteresis. It was only 2 transistors and some resistors. I was able to plot the cut out and recovery temperatures v battery voltage v value of set resistor in a matter of minutes (ok hours if you include setting up the model).
My earliest mentor was an IC designer – there everything was 100% simulated even in the 80s. These days it is a tool that is called for in some situations. I am glad I had the simulation impressed on me at an early age – it is not easy – and it is often expensive – but can also be very valuable.
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